set_property PACKAGE_PIN AR35 [get_ports GPIO_LED_4_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_4_LS]
#NET  3N787                     LOC = AY34 | IOSTANDARD=LVCMOS18; # Bank  13 VCCO - VCC1V8_FPGA - IO_L1P_T0_13
set_property PACKAGE_PIN BA35 [get_ports USB_SMSC_NXT]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_NXT]
set_property PACKAGE_PIN AV36 [get_ports USB_SMSC_DATA0]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA0]
set_property PACKAGE_PIN AW36 [get_ports USB_SMSC_DATA1]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA1]
set_property PACKAGE_PIN BA34 [get_ports USB_SMSC_DATA2]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA2]
set_property PACKAGE_PIN BB34 [get_ports USB_SMSC_DATA3]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA3]
set_property PACKAGE_PIN BA36 [get_ports USB_SMSC_DATA4]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA4]
set_property PACKAGE_PIN BB36 [get_ports USB_SMSC_RESET_B]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_RESET_B]
set_property PACKAGE_PIN BB32 [get_ports USB_SMSC_STP]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_STP]
set_property PACKAGE_PIN BB33 [get_ports USB_SMSC_DIR]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DIR]
set_property PACKAGE_PIN AW35 [get_ports USB_SMSC_DATA7]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA7]
set_property PACKAGE_PIN AY35 [get_ports USB_SMSC_DATA6]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA6]
set_property PACKAGE_PIN AT34 [get_ports USB_SMSC_DATA5]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA5]
set_property PACKAGE_PIN AU34 [get_ports SI5324_INT_ALM_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SI5324_INT_ALM_LS]
set_property PACKAGE_PIN AT36 [get_ports SI5324_RST_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SI5324_RST_LS]
set_property PACKAGE_PIN AU36 [get_ports USB_UART_RX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
set_property PACKAGE_PIN AT32 [get_ports USB_UART_RTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
set_property PACKAGE_PIN AU33 [get_ports USB_UART_TX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
set_property PACKAGE_PIN AR34 [get_ports USB_UART_CTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
set_property PACKAGE_PIN AT35 [get_ports IIC_SCL_MAIN_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_SCL_MAIN_LS]
set_property PACKAGE_PIN AU32 [get_ports IIC_SDA_MAIN_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_SDA_MAIN_LS]
set_property PACKAGE_PIN AV33 [get_ports PCIE_WAKE_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PCIE_WAKE_B_LS]
set_property PACKAGE_PIN AW32 [get_ports REC_CLOCK_C_P]
set_property IOSTANDARD LVCMOS18 [get_ports REC_CLOCK_C_P]
set_property PACKAGE_PIN AW33 [get_ports REC_CLOCK_C_N]
set_property IOSTANDARD LVCMOS18 [get_ports REC_CLOCK_C_N]
set_property PACKAGE_PIN AV34 [get_ports USB_SMSC_REFCLK_OPTION]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_REFCLK_OPTION]
set_property PACKAGE_PIN AV35 [get_ports PCIE_PERST_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PCIE_PERST_LS]
set_property PACKAGE_PIN AY32 [get_ports USB_SMSC_CLKOUT]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_CLKOUT]
set_property PACKAGE_PIN AY33 [get_ports GPIO_DIP_SW1]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW1]
set_property PACKAGE_PIN BA31 [get_ports GPIO_DIP_SW2]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW2]
set_property PACKAGE_PIN BA32 [get_ports GPIO_DIP_SW3]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW3]
set_property PACKAGE_PIN AW30 [get_ports GPIO_DIP_SW4]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW4]
set_property PACKAGE_PIN AY30 [get_ports GPIO_DIP_SW5]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW5]
set_property PACKAGE_PIN BA30 [get_ports GPIO_DIP_SW6]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW6]
set_property PACKAGE_PIN BB31 [get_ports GPIO_DIP_SW7]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW7]
set_property PACKAGE_PIN AV30 [get_ports GPIO_DIP_SW0]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW0]
set_property PACKAGE_PIN AW31 [get_ports ROTARY_PUSH]
set_property IOSTANDARD LVCMOS18 [get_ports ROTARY_PUSH]
set_property PACKAGE_PIN AR30 [get_ports SDIO_DAT0_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_DAT0_LS]
set_property PACKAGE_PIN AT30 [get_ports SDIO_CD_DAT3_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_CD_DAT3_LS]
set_property PACKAGE_PIN AU31 [get_ports SDIO_DAT1_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_DAT1_LS]
set_property PACKAGE_PIN AV31 [get_ports SDIO_DAT2_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_DAT2_LS]
set_property PACKAGE_PIN AN30 [get_ports SDIO_CLK_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_CLK_LS]
set_property PACKAGE_PIN AP30 [get_ports SDIO_CMD_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_CMD_LS]
set_property PACKAGE_PIN AP32 [get_ports SDIO_SDDET]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_SDDET]
set_property PACKAGE_PIN AR32 [get_ports SDIO_SDWP]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_SDWP]
set_property PACKAGE_PIN AN31 [get_ports USER_SMA_GPIO_P]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_GPIO_P]
set_property PACKAGE_PIN AP31 [get_ports USER_SMA_GPIO_N]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_GPIO_N]
set_property PACKAGE_PIN AP33 [get_ports SFP_TX_DISABLE]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_TX_DISABLE]
set_property PACKAGE_PIN AR33 [get_ports ROTARY_INCA]
set_property IOSTANDARD LVCMOS18 [get_ports ROTARY_INCA]
set_property PACKAGE_PIN AT31 [get_ports ROTARY_INCB]
set_property IOSTANDARD LVCMOS18 [get_ports ROTARY_INCB]
set_property PACKAGE_PIN AH35 [get_ports FMC_VADJ_ON_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports FMC_VADJ_ON_B_LS]
set_property PACKAGE_PIN AM36 [get_ports FLASH_D0]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D0]
set_property PACKAGE_PIN AN36 [get_ports FLASH_D1]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D1]
set_property PACKAGE_PIN AJ36 [get_ports FLASH_D2]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D2]
set_property PACKAGE_PIN AJ37 [get_ports FLASH_D3]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D3]
#NET  4N749                     LOC = AP36 | IOSTANDARD=LVCMOS18; # Bank  14 VCCO - VCC1V8_FPGA - IO_L3P_T0_DQS_PUDC_B_14
set_property PACKAGE_PIN AP37 [get_ports FPGA_EMCCLK]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_EMCCLK]
set_property PACKAGE_PIN AK37 [get_ports FLASH_D4]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D4]
set_property PACKAGE_PIN AL37 [get_ports FLASH_D5]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D5]
set_property PACKAGE_PIN AN35 [get_ports FLASH_D6]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D6]
set_property PACKAGE_PIN AP35 [get_ports FLASH_D7]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D7]
set_property PACKAGE_PIN AL36 [get_ports FLASH_CE_B]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_CE_B]
set_property PACKAGE_PIN AM37 [get_ports FLASH_D8]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D8]
set_property PACKAGE_PIN AG33 [get_ports FLASH_D9]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D9]
set_property PACKAGE_PIN AH33 [get_ports FLASH_D10]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D10]
set_property PACKAGE_PIN AK35 [get_ports FLASH_D11]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D11]
set_property PACKAGE_PIN AL35 [get_ports FLASH_D12]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D12]
set_property PACKAGE_PIN AH31 [get_ports PHY_MDC_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDC_LS]
set_property PACKAGE_PIN AJ31 [get_ports FLASH_D13]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D13]
set_property PACKAGE_PIN AH34 [get_ports FLASH_D14]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D14]
set_property PACKAGE_PIN AJ35 [get_ports FLASH_D15]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D15]
set_property PACKAGE_PIN AJ33 [get_ports PHY_RESET_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_LS]
set_property PACKAGE_PIN AK33 [get_ports PHY_MDIO_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDIO_LS]
set_property PACKAGE_PIN AK34 [get_ports USER_CLOCK_P]
set_property IOSTANDARD LVDS [get_ports USER_CLOCK_P]
set_property PACKAGE_PIN AL34 [get_ports USER_CLOCK_N]
set_property IOSTANDARD LVDS [get_ports USER_CLOCK_N]
set_property PACKAGE_PIN AJ32 [get_ports USER_SMA_CLOCK_P]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_CLOCK_P]
set_property PACKAGE_PIN AK32 [get_ports USER_SMA_CLOCK_N]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_CLOCK_N]
set_property PACKAGE_PIN AL31 [get_ports PHY_INT_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_INT_LS]
set_property PACKAGE_PIN AL32 [get_ports FMC_C2M_PG_LS]
set_property IOSTANDARD LVCMOS18 [get_ports FMC_C2M_PG_LS]
set_property PACKAGE_PIN AM34 [get_ports FLASH_WAIT]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_WAIT]
set_property PACKAGE_PIN AN34 [get_ports FMC1_HPC_PG_M2C_LS]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_PG_M2C_LS]
set_property PACKAGE_PIN AM31 [get_ports FMC1_HPC_PRSNT_M2C_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_PRSNT_M2C_B_LS]
set_property PACKAGE_PIN AM32 [get_ports FLASH_A15]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A15]
set_property PACKAGE_PIN AM33 [get_ports FLASH_A14]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A14]
set_property PACKAGE_PIN AN33 [get_ports FLASH_A13]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A13]
set_property PACKAGE_PIN AL29 [get_ports FLASH_A12]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A12]
set_property PACKAGE_PIN AL30 [get_ports FLASH_A11]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A11]
set_property PACKAGE_PIN AH29 [get_ports FLASH_A10]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A10]
set_property PACKAGE_PIN AH30 [get_ports FLASH_A9]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A9]
set_property PACKAGE_PIN AJ30 [get_ports FLASH_A8]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A8]
set_property PACKAGE_PIN AK30 [get_ports FLASH_A7]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A7]
set_property PACKAGE_PIN AF29 [get_ports FMC2_HPC_PG_M2C_LS]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_PG_M2C_LS]
set_property PACKAGE_PIN AG29 [get_ports FLASH_A6]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A6]
set_property PACKAGE_PIN AK28 [get_ports FLASH_A5]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A5]
set_property PACKAGE_PIN AK29 [get_ports FLASH_A4]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A4]
set_property PACKAGE_PIN AF30 [get_ports FLASH_A3]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A3]
set_property PACKAGE_PIN AG31 [get_ports FLASH_A2]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A2]
set_property PACKAGE_PIN AH28 [get_ports FLASH_A1]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A1]
set_property PACKAGE_PIN AJ28 [get_ports FLASH_A0]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A0]
set_property PACKAGE_PIN AG32 [get_ports FMC2_HPC_PRSNT_M2C_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_PRSNT_M2C_B_LS]
#NET  VRN_15                    LOC = AM38 | IOSTANDARD=LVCMOS18; # Bank  15 VCCO - VCC1V8_FPGA - IO_0_VRN_15
set_property PACKAGE_PIN AN38 [get_ports XADC_VAUX0P_R]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_VAUX0P_R]
set_property PACKAGE_PIN AP38 [get_ports XADC_VAUX0N_R]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_VAUX0N_R]
set_property PACKAGE_PIN AM41 [get_ports XADC_VAUX8P_R]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_VAUX8P_R]
set_property PACKAGE_PIN AM42 [get_ports XADC_VAUX8N_R]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_VAUX8N_R]
set_property PACKAGE_PIN AR38 [get_ports LCD_DB5_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB5_LS]
set_property PACKAGE_PIN AR39 [get_ports LCD_DB6_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB6_LS]
set_property PACKAGE_PIN AN40 [get_ports LCD_DB7_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB7_LS]
set_property PACKAGE_PIN AN41 [get_ports LCD_RS_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_RS_LS]
set_property PACKAGE_PIN AR37 [get_ports GPIO_LED_2_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_2_LS]
set_property PACKAGE_PIN AT37 [get_ports GPIO_LED_3_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_3_LS]
set_property PACKAGE_PIN AM39 [get_ports GPIO_LED_0_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_0_LS]
set_property PACKAGE_PIN AN39 [get_ports GPIO_LED_1_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_1_LS]
set_property PACKAGE_PIN AP40 [get_ports GPIO_SW_S]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_SW_S]
set_property PACKAGE_PIN AR40 [get_ports GPIO_SW_N]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_SW_N]
set_property PACKAGE_PIN AP41 [get_ports GPIO_LED_5_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_5_LS]
set_property PACKAGE_PIN AP42 [get_ports GPIO_LED_6_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_6_LS]
#NET  4N920                     LOC = AT39 | IOSTANDARD=LVCMOS18; # Bank  15 VCCO - VCC1V8_FPGA - IO_L9P_T1_DQS_AD3P_15
set_property PACKAGE_PIN AT40 [get_ports LCD_E_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_E_LS]
set_property PACKAGE_PIN AR42 [get_ports LCD_RW_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_RW_LS]
set_property PACKAGE_PIN AT42 [get_ports LCD_DB4_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB4_LS]
set_property PACKAGE_PIN AU39 [get_ports GPIO_LED_7_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_7_LS]
set_property PACKAGE_PIN AV39 [get_ports GPIO_SW_C]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_SW_C]
set_property PACKAGE_PIN AU38 [get_ports GPIO_SW_E]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_SW_E]
set_property PACKAGE_PIN AV38 [get_ports PMBUS_ALERT_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PMBUS_ALERT_LS]
set_property PACKAGE_PIN AV40 [get_ports CPU_RESET]
set_property IOSTANDARD LVCMOS18 [get_ports CPU_RESET]
set_property PACKAGE_PIN AW40 [get_ports GPIO_SW_W]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_SW_W]
set_property PACKAGE_PIN AY39 [get_ports PMBUS_DATA_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PMBUS_DATA_LS]
#NET  4N923                     LOC = AY40 | IOSTANDARD=LVCMOS18; # Bank  15 VCCO - VCC1V8_FPGA - IO_L14N_T2_SRCC_15
set_property PACKAGE_PIN AW37 [get_ports PMBUS_CLK_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PMBUS_CLK_LS]
set_property PACKAGE_PIN AY37 [get_ports FLASH_ADV_B]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_ADV_B]
set_property PACKAGE_PIN BA37 [get_ports SM_FAN_PWM]
set_property IOSTANDARD LVCMOS18 [get_ports SM_FAN_PWM]
set_property PACKAGE_PIN BB37 [get_ports SM_FAN_TACH]
set_property IOSTANDARD LVCMOS18 [get_ports SM_FAN_TACH]
#NET  4N917                     LOC = AW38 | IOSTANDARD=LVCMOS18; # Bank  15 VCCO - VCC1V8_FPGA - IO_L17P_T2_A26_15
#NET  4N916                     LOC = AY38 | IOSTANDARD=LVCMOS18; # Bank  15 VCCO - VCC1V8_FPGA - IO_L17N_T2_A25_15
set_property PACKAGE_PIN BB38 [get_ports SFP_LOS_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_LOS_LS]
set_property PACKAGE_PIN BB39 [get_ports FLASH_A23]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A23]
set_property PACKAGE_PIN BA39 [get_ports FLASH_A22]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A22]
set_property PACKAGE_PIN BA40 [get_ports FLASH_A21]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A21]
set_property PACKAGE_PIN AT41 [get_ports FLASH_A20]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A20]
set_property PACKAGE_PIN AU42 [get_ports FLASH_A19]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A19]
set_property PACKAGE_PIN AY42 [get_ports IIC_MUX_RESET_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_MUX_RESET_B_LS]
set_property PACKAGE_PIN BA42 [get_ports FLASH_A18]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A18]
set_property PACKAGE_PIN AU41 [get_ports FLASH_A17]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A17]
set_property PACKAGE_PIN AV41 [get_ports FLASH_A16]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A16]
set_property PACKAGE_PIN BA41 [get_ports FLASH_OE_B]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_OE_B]
set_property PACKAGE_PIN BB41 [get_ports FLASH_FWE_B]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_FWE_B]
set_property PACKAGE_PIN AW41 [get_ports FLASH_A25]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A25]
set_property PACKAGE_PIN AW42 [get_ports FLASH_A24]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A24]
#NET  VRP_15                    LOC = AU37 | IOSTANDARD=LVCMOS18; # Bank  15 VCCO - VCC1V8_FPGA - IO_25_VRP_15
#NET  5N825                     LOC = Y34  | IOSTANDARD=LVCMOS18; # Bank  16 VCCO - VADJ_FPGA - IO_0_VRN_16
set_property PACKAGE_PIN AF35 [get_ports FMC2_HPC_HA14_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA14_P]
set_property PACKAGE_PIN AF36 [get_ports FMC2_HPC_HA14_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA14_N]
set_property PACKAGE_PIN AE37 [get_ports FMC2_HPC_HA15_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA15_P]
set_property PACKAGE_PIN AF37 [get_ports FMC2_HPC_HA15_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA15_N]
set_property PACKAGE_PIN AF34 [get_ports FMC2_HPC_HA12_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA12_P]
set_property PACKAGE_PIN AG34 [get_ports FMC2_HPC_HA12_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA12_N]
set_property PACKAGE_PIN AD36 [get_ports FMC2_HPC_HA20_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA20_P]
set_property PACKAGE_PIN AD37 [get_ports FMC2_HPC_HA20_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA20_N]
set_property PACKAGE_PIN AC35 [get_ports FMC2_HPC_HA19_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA19_P]
set_property PACKAGE_PIN AC36 [get_ports FMC2_HPC_HA19_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA19_N]
set_property PACKAGE_PIN AG36 [get_ports FMC2_HPC_HA16_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA16_P]
set_property PACKAGE_PIN AH36 [get_ports FMC2_HPC_HA16_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA16_N]
set_property PACKAGE_PIN Y37 [get_ports FMC2_HPC_HA23_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA23_P]
set_property PACKAGE_PIN AA37 [get_ports FMC2_HPC_HA23_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA23_N]
set_property PACKAGE_PIN Y35 [get_ports FMC2_HPC_HA22_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA22_P]
set_property PACKAGE_PIN AA36 [get_ports FMC2_HPC_HA22_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA22_N]
set_property PACKAGE_PIN AB36 [get_ports FMC2_HPC_HA18_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA18_P]
set_property PACKAGE_PIN AB37 [get_ports FMC2_HPC_HA18_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA18_N]
set_property PACKAGE_PIN AA34 [get_ports FMC2_HPC_HA21_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA21_P]
set_property PACKAGE_PIN AA35 [get_ports FMC2_HPC_HA21_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA21_N]
set_property PACKAGE_PIN AB31 [get_ports FMC2_HPC_HA06_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA06_P]
set_property PACKAGE_PIN AB32 [get_ports FMC2_HPC_HA06_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA06_N]
set_property PACKAGE_PIN AB33 [get_ports FMC2_HPC_HA00_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA00_CC_P]
set_property PACKAGE_PIN AC33 [get_ports FMC2_HPC_HA00_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA00_CC_N]
set_property PACKAGE_PIN AD32 [get_ports FMC2_HPC_HA01_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA01_CC_P]
set_property PACKAGE_PIN AD33 [get_ports FMC2_HPC_HA01_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA01_CC_N]
set_property PACKAGE_PIN AC34 [get_ports FMC2_HPC_HA17_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA17_CC_P]
set_property PACKAGE_PIN AD35 [get_ports FMC2_HPC_HA17_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA17_CC_N]
set_property PACKAGE_PIN AE32 [get_ports FMC2_HPC_HA13_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA13_P]
set_property PACKAGE_PIN AE33 [get_ports FMC2_HPC_HA13_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA13_N]
set_property PACKAGE_PIN AF31 [get_ports FMC2_HPC_HA10_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA10_P]
set_property PACKAGE_PIN AF32 [get_ports FMC2_HPC_HA10_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA10_N]
set_property PACKAGE_PIN AE34 [get_ports FMC2_HPC_HA11_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA11_P]
set_property PACKAGE_PIN AE35 [get_ports FMC2_HPC_HA11_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA11_N]
set_property PACKAGE_PIN AE29 [get_ports FMC2_HPC_HA09_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA09_P]
set_property PACKAGE_PIN AE30 [get_ports FMC2_HPC_HA09_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA09_N]
set_property PACKAGE_PIN Y32 [get_ports FMC2_HPC_HA05_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA05_P]
set_property PACKAGE_PIN Y33 [get_ports FMC2_HPC_HA05_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA05_N]
set_property PACKAGE_PIN AC31 [get_ports FMC2_HPC_HA07_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA07_P]
set_property PACKAGE_PIN AD31 [get_ports FMC2_HPC_HA07_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA07_N]
set_property PACKAGE_PIN AA31 [get_ports FMC2_HPC_HA08_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA08_P]
set_property PACKAGE_PIN AA32 [get_ports FMC2_HPC_HA08_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA08_N]
set_property PACKAGE_PIN AC30 [get_ports FMC2_HPC_HA02_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA02_P]
set_property PACKAGE_PIN AD30 [get_ports FMC2_HPC_HA02_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA02_N]
set_property PACKAGE_PIN AA29 [get_ports FMC2_HPC_HA03_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA03_P]
set_property PACKAGE_PIN AA30 [get_ports FMC2_HPC_HA03_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA03_N]
set_property PACKAGE_PIN AB29 [get_ports FMC2_HPC_HA04_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA04_P]
set_property PACKAGE_PIN AC29 [get_ports FMC2_HPC_HA04_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_HA04_N]
#NET  5N826                     LOC = AB34 | IOSTANDARD=LVCMOS18; # Bank  16 VCCO - VADJ_FPGA - IO_25_VRP_16
#NET  5N830                     LOC = Y38  | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_0_VRN_17
set_property PACKAGE_PIN AB41 [get_ports FMC2_HPC_LA10_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA10_P]
set_property PACKAGE_PIN AB42 [get_ports FMC2_HPC_LA10_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA10_N]
set_property PACKAGE_PIN W40 [get_ports FMC2_HPC_LA13_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA13_P]
set_property PACKAGE_PIN Y40 [get_ports FMC2_HPC_LA13_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA13_N]
set_property PACKAGE_PIN Y39 [get_ports FMC2_HPC_LA12_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA12_P]
set_property PACKAGE_PIN AA39 [get_ports FMC2_HPC_LA12_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA12_N]
set_property PACKAGE_PIN Y42 [get_ports FMC2_HPC_LA11_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA11_P]
set_property PACKAGE_PIN AA42 [get_ports FMC2_HPC_LA11_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA11_N]
set_property PACKAGE_PIN AB38 [get_ports FMC2_HPC_LA14_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA14_P]
set_property PACKAGE_PIN AB39 [get_ports FMC2_HPC_LA14_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA14_N]
#NET  5N961                     LOC = AA40 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L6P_T0_17
#NET  5N962                     LOC = AA41 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_17
set_property PACKAGE_PIN AC38 [get_ports FMC2_HPC_LA15_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA15_P]
set_property PACKAGE_PIN AC39 [get_ports FMC2_HPC_LA15_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA15_N]
set_property PACKAGE_PIN AD42 [get_ports FMC2_HPC_LA08_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA08_P]
set_property PACKAGE_PIN AE42 [get_ports FMC2_HPC_LA08_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA08_N]
set_property PACKAGE_PIN AD38 [get_ports FMC2_HPC_LA06_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA06_P]
set_property PACKAGE_PIN AE38 [get_ports FMC2_HPC_LA06_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA06_N]
set_property PACKAGE_PIN AC40 [get_ports FMC2_HPC_LA07_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA07_P]
set_property PACKAGE_PIN AC41 [get_ports FMC2_HPC_LA07_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA07_N]
#NET  5N964                     LOC = AE39 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_17
#NET  5N963                     LOC = AE40 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_17
set_property PACKAGE_PIN AD40 [get_ports FMC2_HPC_LA00_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA00_CC_P]
set_property PACKAGE_PIN AD41 [get_ports FMC2_HPC_LA00_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA00_CC_N]
set_property PACKAGE_PIN AF39 [get_ports FMC2_HPC_CLK0_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_CLK0_M2C_P]
set_property PACKAGE_PIN AF40 [get_ports FMC2_HPC_CLK0_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_CLK0_M2C_N]
set_property PACKAGE_PIN AF41 [get_ports FMC2_HPC_LA01_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA01_CC_P]
set_property PACKAGE_PIN AG41 [get_ports FMC2_HPC_LA01_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA01_CC_N]
#NET  5N959                     LOC = AG39 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L15P_T2_DQS_17
#NET  5N960                     LOC = AH39 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_17
set_property PACKAGE_PIN AF42 [get_ports FMC2_HPC_LA05_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA05_P]
set_property PACKAGE_PIN AG42 [get_ports FMC2_HPC_LA05_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA05_N]
#NET  5N957                     LOC = AG38 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L17P_T2_17
#NET  5N958                     LOC = AH38 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L17N_T2_17
set_property PACKAGE_PIN AJ38 [get_ports FMC2_HPC_LA09_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA09_P]
set_property PACKAGE_PIN AK38 [get_ports FMC2_HPC_LA09_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA09_N]
#NET  5N953                     LOC = AK40 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L19P_T3_17
#NET  5N954                     LOC = AL40 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L19N_T3_VREF_17
#NET  5N955                     LOC = AH40 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L20P_T3_17
#NET  5N956                     LOC = AH41 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_L20N_T3_17
set_property PACKAGE_PIN AL41 [get_ports FMC2_HPC_LA04_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA04_P]
set_property PACKAGE_PIN AL42 [get_ports FMC2_HPC_LA04_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA04_N]
set_property PACKAGE_PIN AJ40 [get_ports FMC2_HPC_LA16_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA16_P]
set_property PACKAGE_PIN AJ41 [get_ports FMC2_HPC_LA16_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA16_N]
set_property PACKAGE_PIN AK39 [get_ports FMC2_HPC_LA02_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA02_P]
set_property PACKAGE_PIN AL39 [get_ports FMC2_HPC_LA02_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA02_N]
set_property PACKAGE_PIN AJ42 [get_ports FMC2_HPC_LA03_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA03_P]
set_property PACKAGE_PIN AK42 [get_ports FMC2_HPC_LA03_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA03_N]
#NET  5N829                     LOC = AG37 | IOSTANDARD=LVCMOS18; # Bank  17 VCCO - VADJ_FPGA - IO_25_VRP_17
#NET  6N1095                    LOC = N35  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_0_VRN_18
#NET  6N1094                    LOC = T34  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L1P_T0_18
#NET  6N1093                    LOC = R35  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L1N_T0_18
set_property PACKAGE_PIN N33 [get_ports FMC2_HPC_LA26_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA26_P]
set_property PACKAGE_PIN N34 [get_ports FMC2_HPC_LA26_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA26_N]
set_property PACKAGE_PIN R33 [get_ports FMC2_HPC_LA25_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA25_P]
set_property PACKAGE_PIN R34 [get_ports FMC2_HPC_LA25_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA25_N]
set_property PACKAGE_PIN P35 [get_ports FMC2_HPC_LA21_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA21_P]
set_property PACKAGE_PIN P36 [get_ports FMC2_HPC_LA21_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA21_N]
set_property PACKAGE_PIN T32 [get_ports FMC2_HPC_LA30_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA30_P]
set_property PACKAGE_PIN R32 [get_ports FMC2_HPC_LA30_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA30_N]
set_property PACKAGE_PIN P32 [get_ports FMC2_HPC_LA27_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA27_P]
set_property PACKAGE_PIN P33 [get_ports FMC2_HPC_LA27_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA27_N]
set_property PACKAGE_PIN T36 [get_ports FMC2_HPC_LA33_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA33_P]
set_property PACKAGE_PIN R37 [get_ports FMC2_HPC_LA33_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA33_N]
set_property PACKAGE_PIN P37 [get_ports FMC2_HPC_LA32_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA32_P]
set_property PACKAGE_PIN P38 [get_ports FMC2_HPC_LA32_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA32_N]
set_property PACKAGE_PIN U34 [get_ports FMC2_HPC_LA24_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA24_P]
set_property PACKAGE_PIN T35 [get_ports FMC2_HPC_LA24_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA24_N]
set_property PACKAGE_PIN R38 [get_ports FMC2_HPC_LA23_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA23_P]
set_property PACKAGE_PIN R39 [get_ports FMC2_HPC_LA23_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA23_N]
set_property PACKAGE_PIN U37 [get_ports FMC2_HPC_LA17_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA17_CC_P]
set_property PACKAGE_PIN U38 [get_ports FMC2_HPC_LA17_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA17_CC_N]
set_property PACKAGE_PIN U39 [get_ports FMC2_HPC_CLK1_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_CLK1_M2C_P]
set_property PACKAGE_PIN T39 [get_ports FMC2_HPC_CLK1_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_CLK1_M2C_N]
set_property PACKAGE_PIN U36 [get_ports FMC2_HPC_LA18_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA18_CC_P]
set_property PACKAGE_PIN T37 [get_ports FMC2_HPC_LA18_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA18_CC_N]
set_property PACKAGE_PIN V35 [get_ports FMC2_HPC_LA28_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA28_P]
set_property PACKAGE_PIN V36 [get_ports FMC2_HPC_LA28_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA28_N]
set_property PACKAGE_PIN V33 [get_ports FMC2_HPC_LA20_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA20_P]
set_property PACKAGE_PIN V34 [get_ports FMC2_HPC_LA20_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA20_N]
set_property PACKAGE_PIN W36 [get_ports FMC2_HPC_LA29_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA29_P]
set_property PACKAGE_PIN W37 [get_ports FMC2_HPC_LA29_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA29_N]
set_property PACKAGE_PIN U32 [get_ports FMC2_HPC_LA19_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA19_P]
set_property PACKAGE_PIN U33 [get_ports FMC2_HPC_LA19_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA19_N]
set_property PACKAGE_PIN W32 [get_ports FMC2_HPC_LA22_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA22_P]
set_property PACKAGE_PIN W33 [get_ports FMC2_HPC_LA22_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA22_N]
set_property PACKAGE_PIN V39 [get_ports FMC2_HPC_LA31_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA31_P]
set_property PACKAGE_PIN V40 [get_ports FMC2_HPC_LA31_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_HPC_LA31_N]
#NET  6N1047                    LOC = T40  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L20P_T3_18
#NET  6N1048                    LOC = T41  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L20N_T3_18
#NET  6N1024                    LOC = W41  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L21P_T3_DQS_18
#NET  6N1025                    LOC = W42  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L21N_T3_DQS_18
#NET  6N1027                    LOC = U41  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L22P_T3_18
#NET  6N1026                    LOC = T42  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L22N_T3_18
#NET  6N1031                    LOC = W38  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L23P_T3_18
#NET  6N1030                    LOC = V38  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L23N_T3_18
#NET  6N1028                    LOC = V41  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L24P_T3_18
#NET  6N1029                    LOC = U42  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_L24N_T3_18
#NET  6N1023                    LOC = W35  | IOSTANDARD=LVCMOS18; # Bank  18 VCCO - VADJ_FPGA - IO_25_VRP_18
#NET  VRN_19                    LOC = L36  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_0_VRN_19
#NET  6N957                     LOC = E40  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L1P_T0_19
#NET  6N958                     LOC = D40  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L1N_T0_19
#NET  6N959                     LOC = A40  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L2P_T0_19
#NET  6N960                     LOC = A41  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L2N_T0_19
#NET  6N961                     LOC = D41  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_19
#NET  6N963                     LOC = D42  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_19
#NET  6N962                     LOC = B41  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L4P_T0_19
#NET  6N964                     LOC = B42  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L4N_T0_19
#NET  6N967                     LOC = F42  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L5P_T0_19
#NET  6N968                     LOC = E42  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L5N_T0_19
#NET  6N969                     LOC = C40  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L6P_T0_19
#NET  6N970                     LOC = C41  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_19
set_property PACKAGE_PIN H40 [get_ports FMC1_HPC_LA04_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA04_P]
set_property PACKAGE_PIN H41 [get_ports FMC1_HPC_LA04_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA04_N]
set_property PACKAGE_PIN H39 [get_ports FMC1_HPC_LA13_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA13_P]
set_property PACKAGE_PIN G39 [get_ports FMC1_HPC_LA13_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA13_N]
set_property PACKAGE_PIN G41 [get_ports FMC1_HPC_LA07_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA07_P]
set_property PACKAGE_PIN G42 [get_ports FMC1_HPC_LA07_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA07_N]
set_property PACKAGE_PIN F40 [get_ports FMC1_HPC_LA11_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA11_P]
set_property PACKAGE_PIN F41 [get_ports FMC1_HPC_LA11_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA11_N]
set_property PACKAGE_PIN J40 [get_ports FMC1_HPC_LA01_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA01_CC_P]
set_property PACKAGE_PIN J41 [get_ports FMC1_HPC_LA01_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA01_CC_N]
set_property PACKAGE_PIN K39 [get_ports FMC1_HPC_LA00_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA00_CC_P]
set_property PACKAGE_PIN K40 [get_ports FMC1_HPC_LA00_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA00_CC_N]
set_property PACKAGE_PIN L39 [get_ports FMC1_HPC_CLK0_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_CLK0_M2C_P]
set_property PACKAGE_PIN L40 [get_ports FMC1_HPC_CLK0_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_CLK0_M2C_N]
set_property PACKAGE_PIN M41 [get_ports FMC1_HPC_LA05_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA05_P]
set_property PACKAGE_PIN L41 [get_ports FMC1_HPC_LA05_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA05_N]
set_property PACKAGE_PIN K42 [get_ports FMC1_HPC_LA06_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA06_P]
set_property PACKAGE_PIN J42 [get_ports FMC1_HPC_LA06_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA06_N]
set_property PACKAGE_PIN M42 [get_ports FMC1_HPC_LA03_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA03_P]
set_property PACKAGE_PIN L42 [get_ports FMC1_HPC_LA03_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA03_N]
set_property PACKAGE_PIN K37 [get_ports FMC1_HPC_LA16_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA16_P]
set_property PACKAGE_PIN K38 [get_ports FMC1_HPC_LA16_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA16_N]
set_property PACKAGE_PIN M36 [get_ports FMC1_HPC_LA15_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA15_P]
set_property PACKAGE_PIN L37 [get_ports FMC1_HPC_LA15_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA15_N]
set_property PACKAGE_PIN P41 [get_ports FMC1_HPC_LA02_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA02_P]
set_property PACKAGE_PIN N41 [get_ports FMC1_HPC_LA02_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA02_N]
set_property PACKAGE_PIN M37 [get_ports FMC1_HPC_LA08_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA08_P]
set_property PACKAGE_PIN M38 [get_ports FMC1_HPC_LA08_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA08_N]
set_property PACKAGE_PIN R42 [get_ports FMC1_HPC_LA09_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA09_P]
set_property PACKAGE_PIN P42 [get_ports FMC1_HPC_LA09_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA09_N]
set_property PACKAGE_PIN N38 [get_ports FMC1_HPC_LA10_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA10_P]
set_property PACKAGE_PIN M39 [get_ports FMC1_HPC_LA10_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA10_N]
set_property PACKAGE_PIN R40 [get_ports FMC1_HPC_LA12_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA12_P]
set_property PACKAGE_PIN P40 [get_ports FMC1_HPC_LA12_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA12_N]
set_property PACKAGE_PIN N39 [get_ports FMC1_HPC_LA14_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA14_P]
set_property PACKAGE_PIN N40 [get_ports FMC1_HPC_LA14_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA14_N]
#NET  VRP_19                    LOC = N36  | IOSTANDARD=LVCMOS18; # Bank  19 VCCO - VADJ_FPGA - IO_25_VRP_19
#NET  VRN_33                    LOC = AL24 | IOSTANDARD=LVCMOS18; # Bank  33 VCCO - VCC1V8_FPGA - IO_0_VRN_33
set_property PACKAGE_PIN AJ23 [get_ports HDMI_R_D11]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D11]
set_property PACKAGE_PIN AK23 [get_ports HDMI_R_D10]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D10]
set_property PACKAGE_PIN AK20 [get_ports HDMI_R_D9]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D9]
set_property PACKAGE_PIN AL20 [get_ports HDMI_R_D8]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D8]
set_property PACKAGE_PIN AJ22 [get_ports HDMI_R_D7]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D7]
set_property PACKAGE_PIN AK22 [get_ports HDMI_R_D6]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D6]
set_property PACKAGE_PIN AL21 [get_ports HDMI_R_D5]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D5]
set_property PACKAGE_PIN AM21 [get_ports HDMI_R_D4]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D4]
set_property PACKAGE_PIN AJ21 [get_ports HDMI_R_D3]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D3]
set_property PACKAGE_PIN AJ20 [get_ports HDMI_R_D2]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D2]
set_property PACKAGE_PIN AL22 [get_ports HDMI_R_D1]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D1]
set_property PACKAGE_PIN AM22 [get_ports HDMI_R_D0]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D0]
set_property PACKAGE_PIN AM24 [get_ports HDMI_INT]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_INT]
set_property PACKAGE_PIN AN24 [get_ports HDMI_R_D17]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D17]
set_property PACKAGE_PIN AM23 [get_ports HDMI_R_D16]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D16]
set_property PACKAGE_PIN AN23 [get_ports HDMI_R_D15]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D15]
set_property PACKAGE_PIN AP23 [get_ports HDMI_R_D14]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D14]
set_property PACKAGE_PIN AP22 [get_ports HDMI_R_D13]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D13]
set_property PACKAGE_PIN AN21 [get_ports HDMI_R_D12]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D12]
set_property PACKAGE_PIN AP21 [get_ports HDMI_R_DE]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_DE]
set_property PACKAGE_PIN AR23 [get_ports HDMI_R_SPDIF]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_SPDIF]
set_property PACKAGE_PIN AR22 [get_ports HDMI_SPDIF_OUT_LS]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_SPDIF_OUT_LS]
set_property PACKAGE_PIN AT22 [get_ports HDMI_R_VSYNC]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_VSYNC]
set_property PACKAGE_PIN AU22 [get_ports HDMI_R_HSYNC]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_HSYNC]
set_property PACKAGE_PIN AU23 [get_ports HDMI_R_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_CLK]
set_property PACKAGE_PIN AV23 [get_ports HDMI_R_D35]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D35]
set_property PACKAGE_PIN AW23 [get_ports HDMI_R_D34]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D34]
set_property PACKAGE_PIN AW22 [get_ports HDMI_R_D33]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D33]
set_property PACKAGE_PIN AT21 [get_ports HDMI_R_D32]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D32]
set_property PACKAGE_PIN AU21 [get_ports HDMI_R_D31]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D31]
set_property PACKAGE_PIN AR24 [get_ports HDMI_R_D30]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D30]
set_property PACKAGE_PIN AT24 [get_ports HDMI_R_D29]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D29]
set_property PACKAGE_PIN AV21 [get_ports HDMI_R_D28]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D28]
set_property PACKAGE_PIN AW21 [get_ports HDMI_R_D27]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D27]
set_property PACKAGE_PIN AU24 [get_ports HDMI_R_D26]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D26]
set_property PACKAGE_PIN AV24 [get_ports HDMI_R_D25]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D25]
set_property PACKAGE_PIN AY23 [get_ports HDMI_R_D24]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D24]
set_property PACKAGE_PIN AY22 [get_ports HDMI_R_D23]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D23]
set_property PACKAGE_PIN AY25 [get_ports HDMI_R_D22]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D22]
set_property PACKAGE_PIN BA25 [get_ports HDMI_R_D21]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D21]
set_property PACKAGE_PIN BA22 [get_ports HDMI_R_D20]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D20]
set_property PACKAGE_PIN BB22 [get_ports HDMI_R_D19]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D19]
set_property PACKAGE_PIN AY24 [get_ports HDMI_R_D18]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D18]
#NET  7N1099                    LOC = BA24 | IOSTANDARD=LVCMOS18; # Bank  33 VCCO - VCC1V8_FPGA - IO_L22N_T3_33
set_property PACKAGE_PIN BA21 [get_ports XADC_GPIO_0]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_GPIO_0]
set_property PACKAGE_PIN BB21 [get_ports XADC_GPIO_1]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_GPIO_1]
set_property PACKAGE_PIN BB24 [get_ports XADC_GPIO_2]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_GPIO_2]
set_property PACKAGE_PIN BB23 [get_ports XADC_GPIO_3]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_GPIO_3]
#NET  VRP_33                    LOC = AN20 | IOSTANDARD=LVCMOS18; # Bank  33 VCCO - VCC1V8_FPGA - IO_25_VRP_33
#NET  VRN_34                    LOC = R29  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_0_VRN_34
#NET  8N640                     LOC = K35  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L1P_T0_34
#NET  8N641                     LOC = J35  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L1N_T0_34
#NET  8N635                     LOC = J32  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L2P_T0_34
#NET  8N636                     LOC = J33  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L2N_T0_34
#NET  8N637                     LOC = K33  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_34
#NET  8N646                     LOC = K34  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_34
#NET  8N634                     LOC = L34  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L4P_T0_34
#NET  8N649                     LOC = L35  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L4N_T0_34
#NET  8N648                     LOC = M33  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L5P_T0_34
#NET  8N651                     LOC = M34  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L5N_T0_34
#NET  8N650                     LOC = H34  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L6P_T0_34
#NET  8N652                     LOC = H35  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_34
set_property PACKAGE_PIN K29 [get_ports FMC1_HPC_LA25_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA25_P]
set_property PACKAGE_PIN K30 [get_ports FMC1_HPC_LA25_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA25_N]
set_property PACKAGE_PIN J30 [get_ports FMC1_HPC_LA26_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA26_P]
set_property PACKAGE_PIN H30 [get_ports FMC1_HPC_LA26_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA26_N]
set_property PACKAGE_PIN L29 [get_ports FMC1_HPC_LA28_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA28_P]
set_property PACKAGE_PIN L30 [get_ports FMC1_HPC_LA28_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA28_N]
set_property PACKAGE_PIN J31 [get_ports FMC1_HPC_LA27_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA27_P]
set_property PACKAGE_PIN H31 [get_ports FMC1_HPC_LA27_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA27_N]
set_property PACKAGE_PIN M32 [get_ports FMC1_HPC_LA18_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA18_CC_P]
set_property PACKAGE_PIN L32 [get_ports FMC1_HPC_LA18_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA18_CC_N]
set_property PACKAGE_PIN L31 [get_ports FMC1_HPC_LA17_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA17_CC_P]
set_property PACKAGE_PIN K32 [get_ports FMC1_HPC_LA17_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA17_CC_N]
set_property PACKAGE_PIN N30 [get_ports FMC1_HPC_CLK1_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_CLK1_M2C_P]
set_property PACKAGE_PIN M31 [get_ports FMC1_HPC_CLK1_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_CLK1_M2C_N]
set_property PACKAGE_PIN P30 [get_ports FMC1_HPC_LA23_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA23_P]
set_property PACKAGE_PIN N31 [get_ports FMC1_HPC_LA23_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA23_N]
set_property PACKAGE_PIN M28 [get_ports FMC1_HPC_LA31_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA31_P]
set_property PACKAGE_PIN M29 [get_ports FMC1_HPC_LA31_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA31_N]
set_property PACKAGE_PIN R28 [get_ports FMC1_HPC_LA22_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA22_P]
set_property PACKAGE_PIN P28 [get_ports FMC1_HPC_LA22_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA22_N]
set_property PACKAGE_PIN N28 [get_ports FMC1_HPC_LA21_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA21_P]
set_property PACKAGE_PIN N29 [get_ports FMC1_HPC_LA21_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA21_N]
set_property PACKAGE_PIN R30 [get_ports FMC1_HPC_LA24_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA24_P]
set_property PACKAGE_PIN P31 [get_ports FMC1_HPC_LA24_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA24_N]
set_property PACKAGE_PIN U31 [get_ports FMC1_HPC_LA33_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA33_P]
set_property PACKAGE_PIN T31 [get_ports FMC1_HPC_LA33_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA33_N]
set_property PACKAGE_PIN V30 [get_ports FMC1_HPC_LA30_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA30_P]
set_property PACKAGE_PIN V31 [get_ports FMC1_HPC_LA30_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA30_N]
set_property PACKAGE_PIN T29 [get_ports FMC1_HPC_LA29_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA29_P]
set_property PACKAGE_PIN T30 [get_ports FMC1_HPC_LA29_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA29_N]
set_property PACKAGE_PIN W30 [get_ports FMC1_HPC_LA19_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA19_P]
set_property PACKAGE_PIN W31 [get_ports FMC1_HPC_LA19_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA19_N]
set_property PACKAGE_PIN V29 [get_ports FMC1_HPC_LA32_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA32_P]
set_property PACKAGE_PIN U29 [get_ports FMC1_HPC_LA32_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA32_N]
set_property PACKAGE_PIN Y29 [get_ports FMC1_HPC_LA20_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA20_P]
set_property PACKAGE_PIN Y30 [get_ports FMC1_HPC_LA20_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA20_N]
#NET  VRP_34                    LOC = U28  | IOSTANDARD=LVCMOS18; # Bank  34 VCCO - VADJ_FPGA - IO_25_VRP_34
#NET  8N545                     LOC = G31  | IOSTANDARD=LVCMOS18; # Bank  35 VCCO - VADJ_FPGA - IO_0_VRN_35
set_property PACKAGE_PIN B36 [get_ports FMC1_HPC_HA13_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA13_P]
set_property PACKAGE_PIN A37 [get_ports FMC1_HPC_HA13_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA13_N]
set_property PACKAGE_PIN B34 [get_ports FMC1_HPC_HA20_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA20_P]
set_property PACKAGE_PIN A34 [get_ports FMC1_HPC_HA20_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA20_N]
set_property PACKAGE_PIN B39 [get_ports FMC1_HPC_HA16_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA16_P]
set_property PACKAGE_PIN A39 [get_ports FMC1_HPC_HA16_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA16_N]
set_property PACKAGE_PIN A35 [get_ports FMC1_HPC_HA23_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA23_P]
set_property PACKAGE_PIN A36 [get_ports FMC1_HPC_HA23_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA23_N]
set_property PACKAGE_PIN C38 [get_ports FMC1_HPC_HA07_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA07_P]
set_property PACKAGE_PIN C39 [get_ports FMC1_HPC_HA07_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA07_N]
set_property PACKAGE_PIN B37 [get_ports FMC1_HPC_HA12_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA12_P]
set_property PACKAGE_PIN B38 [get_ports FMC1_HPC_HA12_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA12_N]
set_property PACKAGE_PIN E32 [get_ports FMC1_HPC_HA09_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA09_P]
set_property PACKAGE_PIN D32 [get_ports FMC1_HPC_HA09_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA09_N]
set_property PACKAGE_PIN B32 [get_ports FMC1_HPC_HA19_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA19_P]
set_property PACKAGE_PIN B33 [get_ports FMC1_HPC_HA19_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA19_N]
set_property PACKAGE_PIN E33 [get_ports FMC1_HPC_HA02_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA02_P]
set_property PACKAGE_PIN D33 [get_ports FMC1_HPC_HA02_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA02_N]
set_property PACKAGE_PIN C33 [get_ports FMC1_HPC_HA15_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA15_P]
set_property PACKAGE_PIN C34 [get_ports FMC1_HPC_HA15_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA15_N]
set_property PACKAGE_PIN D35 [get_ports FMC1_HPC_HA01_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA01_CC_P]
set_property PACKAGE_PIN D36 [get_ports FMC1_HPC_HA01_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA01_CC_N]
set_property PACKAGE_PIN C35 [get_ports FMC1_HPC_HA17_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA17_CC_P]
set_property PACKAGE_PIN C36 [get_ports FMC1_HPC_HA17_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA17_CC_N]
set_property PACKAGE_PIN E34 [get_ports FMC1_HPC_HA00_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA00_CC_P]
set_property PACKAGE_PIN E35 [get_ports FMC1_HPC_HA00_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA00_CC_N]
set_property PACKAGE_PIN D37 [get_ports FMC1_HPC_HA21_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA21_P]
set_property PACKAGE_PIN D38 [get_ports FMC1_HPC_HA21_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA21_N]
set_property PACKAGE_PIN G32 [get_ports FMC1_HPC_HA05_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA05_P]
set_property PACKAGE_PIN F32 [get_ports FMC1_HPC_HA05_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA05_N]
set_property PACKAGE_PIN F36 [get_ports FMC1_HPC_HA22_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA22_P]
set_property PACKAGE_PIN F37 [get_ports FMC1_HPC_HA22_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA22_N]
set_property PACKAGE_PIN F34 [get_ports FMC1_HPC_HA04_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA04_P]
set_property PACKAGE_PIN F35 [get_ports FMC1_HPC_HA04_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA04_N]
set_property PACKAGE_PIN H33 [get_ports FMC1_HPC_HA03_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA03_P]
set_property PACKAGE_PIN G33 [get_ports FMC1_HPC_HA03_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA03_N]
set_property PACKAGE_PIN E37 [get_ports FMC1_HPC_HA14_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA14_P]
set_property PACKAGE_PIN E38 [get_ports FMC1_HPC_HA14_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA14_N]
set_property PACKAGE_PIN G36 [get_ports FMC1_HPC_HA06_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA06_P]
set_property PACKAGE_PIN G37 [get_ports FMC1_HPC_HA06_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA06_N]
set_property PACKAGE_PIN F39 [get_ports FMC1_HPC_HA18_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA18_P]
set_property PACKAGE_PIN E39 [get_ports FMC1_HPC_HA18_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA18_N]
set_property PACKAGE_PIN J37 [get_ports FMC1_HPC_HA11_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA11_P]
set_property PACKAGE_PIN J38 [get_ports FMC1_HPC_HA11_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA11_N]
set_property PACKAGE_PIN H38 [get_ports FMC1_HPC_HA10_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA10_P]
set_property PACKAGE_PIN G38 [get_ports FMC1_HPC_HA10_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA10_N]
set_property PACKAGE_PIN J36 [get_ports FMC1_HPC_HA08_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA08_P]
set_property PACKAGE_PIN H36 [get_ports FMC1_HPC_HA08_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA08_N]
#NET  8N546                     LOC = G34  | IOSTANDARD=LVCMOS18; # Bank  35 VCCO - VADJ_FPGA - IO_25_VRP_35
#NET  9N472                     LOC = M23  | IOSTANDARD=LVCMOS18; # Bank  36 VCCO - FMC1_VIO_B_M2C - IO_0_VRN_36
set_property PACKAGE_PIN H24 [get_ports FMC1_HPC_HB04_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB04_P]
set_property PACKAGE_PIN G24 [get_ports FMC1_HPC_HB04_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB04_N]
set_property PACKAGE_PIN J21 [get_ports FMC1_HPC_HB14_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB14_P]
set_property PACKAGE_PIN H21 [get_ports FMC1_HPC_HB14_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB14_N]
set_property PACKAGE_PIN H25 [get_ports FMC1_HPC_HB08_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB08_P]
set_property PACKAGE_PIN H26 [get_ports FMC1_HPC_HB08_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB08_N]
set_property PACKAGE_PIN G21 [get_ports FMC1_HPC_HB18_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB18_P]
set_property PACKAGE_PIN G22 [get_ports FMC1_HPC_HB18_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB18_N]
set_property PACKAGE_PIN G26 [get_ports FMC1_HPC_HB07_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB07_P]
set_property PACKAGE_PIN G27 [get_ports FMC1_HPC_HB07_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB07_N]
set_property PACKAGE_PIN H23 [get_ports FMC1_HPC_HB09_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB09_P]
set_property PACKAGE_PIN G23 [get_ports FMC1_HPC_HB09_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB09_N]
set_property PACKAGE_PIN G28 [get_ports FMC1_HPC_HB03_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB03_P]
set_property PACKAGE_PIN G29 [get_ports FMC1_HPC_HB03_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB03_N]
set_property PACKAGE_PIN K28 [get_ports FMC1_HPC_HB02_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB02_P]
set_property PACKAGE_PIN J28 [get_ports FMC1_HPC_HB02_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB02_N]
set_property PACKAGE_PIN H28 [get_ports FMC1_HPC_HB01_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB01_P]
set_property PACKAGE_PIN H29 [get_ports FMC1_HPC_HB01_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB01_N]
set_property PACKAGE_PIN K27 [get_ports FMC1_HPC_HB05_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB05_P]
set_property PACKAGE_PIN J27 [get_ports FMC1_HPC_HB05_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB05_N]
set_property PACKAGE_PIN K24 [get_ports FMC1_HPC_HB12_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB12_P]
set_property PACKAGE_PIN K25 [get_ports FMC1_HPC_HB12_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB12_N]
set_property PACKAGE_PIN J25 [get_ports FMC1_HPC_HB00_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB00_CC_P]
set_property PACKAGE_PIN J26 [get_ports FMC1_HPC_HB00_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB00_CC_N]
set_property PACKAGE_PIN M24 [get_ports FMC1_HPC_HB17_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB17_CC_P]
set_property PACKAGE_PIN L24 [get_ports FMC1_HPC_HB17_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB17_CC_N]
set_property PACKAGE_PIN K23 [get_ports FMC1_HPC_HB06_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB06_CC_P]
set_property PACKAGE_PIN J23 [get_ports FMC1_HPC_HB06_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB06_CC_N]
set_property PACKAGE_PIN M22 [get_ports FMC1_HPC_HB10_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB10_P]
set_property PACKAGE_PIN L22 [get_ports FMC1_HPC_HB10_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB10_N]
set_property PACKAGE_PIN L25 [get_ports FMC1_HPC_HB19_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB19_P]
set_property PACKAGE_PIN L26 [get_ports FMC1_HPC_HB19_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB19_N]
set_property PACKAGE_PIN K22 [get_ports FMC1_HPC_HB11_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB11_P]
set_property PACKAGE_PIN J22 [get_ports FMC1_HPC_HB11_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB11_N]
set_property PACKAGE_PIN M21 [get_ports FMC1_HPC_HB15_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB15_P]
set_property PACKAGE_PIN L21 [get_ports FMC1_HPC_HB15_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB15_N]
set_property PACKAGE_PIN P21 [get_ports FMC1_HPC_HB20_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB20_P]
set_property PACKAGE_PIN N21 [get_ports FMC1_HPC_HB20_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB20_N]
set_property PACKAGE_PIN P25 [get_ports FMC1_HPC_HB13_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB13_P]
set_property PACKAGE_PIN P26 [get_ports FMC1_HPC_HB13_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB13_N]
set_property PACKAGE_PIN P22 [get_ports FMC1_HPC_HB21_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB21_P]
set_property PACKAGE_PIN P23 [get_ports FMC1_HPC_HB21_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB21_N]
set_property PACKAGE_PIN N25 [get_ports FMC1_HPC_HB16_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB16_P]
set_property PACKAGE_PIN N26 [get_ports FMC1_HPC_HB16_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB16_N]
#NET  9N473                     LOC = N23  | IOSTANDARD=LVCMOS18; # Bank  36 VCCO - FMC1_VIO_B_M2C - IO_L23P_T3_36
#NET  9N474                     LOC = N24  | IOSTANDARD=LVCMOS18; # Bank  36 VCCO - FMC1_VIO_B_M2C - IO_L23N_T3_36
#NET  9N475                     LOC = M27  | IOSTANDARD=LVCMOS18; # Bank  36 VCCO - FMC1_VIO_B_M2C - IO_L24P_T3_36
#NET  9N476                     LOC = L27  | IOSTANDARD=LVCMOS18; # Bank  36 VCCO - FMC1_VIO_B_M2C - IO_L24N_T3_36
#NET  9N477                     LOC = M26  | IOSTANDARD=LVCMOS18; # Bank  36 VCCO - FMC1_VIO_B_M2C - IO_25_VRP_36
#NET  VRN_37                    LOC = F21  | IOSTANDARD=SSTL15; # Bank  37 VCCO - VCC1V5_FPGA - IO_0_VRN_37
set_property PACKAGE_PIN A24 [get_ports DDR3_D32]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D32]
set_property PACKAGE_PIN A25 [get_ports DDR3_D38]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D38]
set_property PACKAGE_PIN B22 [get_ports DDR3_D37]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D37]
set_property PACKAGE_PIN A22 [get_ports DDR3_D36]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D36]
set_property PACKAGE_PIN A26 [get_ports DDR3_DQS4_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
set_property PACKAGE_PIN A27 [get_ports DDR3_DQS4_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
set_property PACKAGE_PIN C23 [get_ports DDR3_DM4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
set_property PACKAGE_PIN B23 [get_ports DDR3_D33]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D33]
set_property PACKAGE_PIN B26 [get_ports DDR3_D35]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D35]
set_property PACKAGE_PIN B27 [get_ports DDR3_D34]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D34]
set_property PACKAGE_PIN C24 [get_ports DDR3_D39]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
#NET  VTTVREF                   LOC = B24  | IOSTANDARD=SSTL15; # Bank  37 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_37
set_property PACKAGE_PIN E23 [get_ports DDR3_D44]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
set_property PACKAGE_PIN E24 [get_ports DDR3_D40]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
set_property PACKAGE_PIN F22 [get_ports DDR3_D46]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
set_property PACKAGE_PIN E22 [get_ports DDR3_D47]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
set_property PACKAGE_PIN F25 [get_ports DDR3_DQS5_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
set_property PACKAGE_PIN E25 [get_ports DDR3_DQS5_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
set_property PACKAGE_PIN D22 [get_ports DDR3_D45]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
set_property PACKAGE_PIN D23 [get_ports DDR3_D41]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
set_property PACKAGE_PIN D25 [get_ports DDR3_DM5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
set_property PACKAGE_PIN D26 [get_ports DDR3_D42]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
set_property PACKAGE_PIN C25 [get_ports DDR3_D43]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
#NET  9N541                     LOC = C26  | IOSTANDARD=SSTL15; # Bank  37 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_37
set_property PACKAGE_PIN D27 [get_ports DDR3_D49]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
set_property PACKAGE_PIN D28 [get_ports DDR3_D52]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
set_property PACKAGE_PIN C28 [get_ports DDR3_D51]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
set_property PACKAGE_PIN C29 [get_ports DDR3_RESET_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
set_property PACKAGE_PIN B28 [get_ports DDR3_DQS6_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
set_property PACKAGE_PIN B29 [get_ports DDR3_DQS6_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
set_property PACKAGE_PIN A31 [get_ports DDR3_D54]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
set_property PACKAGE_PIN A32 [get_ports DDR3_D55]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
set_property PACKAGE_PIN A29 [get_ports DDR3_D50]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
set_property PACKAGE_PIN A30 [get_ports DDR3_D48]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
set_property PACKAGE_PIN C31 [get_ports DDR3_DM6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
set_property PACKAGE_PIN B31 [get_ports DDR3_D53]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
set_property PACKAGE_PIN E30 [get_ports DDR3_D56]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
#NET  VTTVREF                   LOC = D31  | IOSTANDARD=SSTL15; # Bank  37 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_37
set_property PACKAGE_PIN D30 [get_ports DDR3_D63]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
set_property PACKAGE_PIN C30 [get_ports DDR3_D60]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
set_property PACKAGE_PIN E27 [get_ports DDR3_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
set_property PACKAGE_PIN E28 [get_ports DDR3_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
set_property PACKAGE_PIN F29 [get_ports DDR3_D57]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
set_property PACKAGE_PIN E29 [get_ports DDR3_D61]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
set_property PACKAGE_PIN F26 [get_ports DDR3_D62]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
set_property PACKAGE_PIN F27 [get_ports DDR3_D59]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
set_property PACKAGE_PIN F30 [get_ports DDR3_D58]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
set_property PACKAGE_PIN F31 [get_ports DDR3_DM7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
#NET  VRP_37                    LOC = F24  | IOSTANDARD=SSTL15; # Bank  37 VCCO - VCC1V5_FPGA - IO_25_VRP_37
#NET  VRN_38                    LOC = K18  | IOSTANDARD=SSTL15; # Bank  38 VCCO - VCC1V5_FPGA - IO_0_VRN_38
set_property PACKAGE_PIN C19 [get_ports DDR3_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
set_property PACKAGE_PIN B19 [get_ports DDR3_A1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
set_property PACKAGE_PIN A16 [get_ports DDR3_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
set_property PACKAGE_PIN A15 [get_ports DDR3_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
set_property PACKAGE_PIN A20 [get_ports DDR3_A0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
set_property PACKAGE_PIN A19 [get_ports DDR3_A3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
set_property PACKAGE_PIN B17 [get_ports DDR3_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
set_property PACKAGE_PIN A17 [get_ports DDR3_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
set_property PACKAGE_PIN B21 [get_ports DDR3_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
set_property PACKAGE_PIN A21 [get_ports DDR3_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
set_property PACKAGE_PIN C18 [get_ports DDR3_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
set_property PACKAGE_PIN B18 [get_ports VTTVREF]
set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
set_property PACKAGE_PIN D20 [get_ports DDR3_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
set_property PACKAGE_PIN C20 [get_ports DDR3_A2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
set_property PACKAGE_PIN F17 [get_ports DDR3_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
set_property PACKAGE_PIN E17 [get_ports DDR3_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
set_property PACKAGE_PIN D21 [get_ports DDR3_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
set_property PACKAGE_PIN C21 [get_ports DDR3_BA1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
set_property PACKAGE_PIN D18 [get_ports DDR3_BA2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
set_property PACKAGE_PIN D17 [get_ports DDR3_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
set_property PACKAGE_PIN G19 [get_ports DDR3_CLK1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
set_property PACKAGE_PIN F19 [get_ports DDR3_CLK1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
set_property PACKAGE_PIN E19 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN E18 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
set_property PACKAGE_PIN H19 [get_ports DDR3_CLK0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
set_property PACKAGE_PIN G18 [get_ports DDR3_CLK0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
set_property PACKAGE_PIN K19 [get_ports DDR3_CKE0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
set_property PACKAGE_PIN J18 [get_ports DDR3_CKE1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
set_property PACKAGE_PIN F20 [get_ports DDR3_WE_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
set_property PACKAGE_PIN E20 [get_ports DDR3_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
set_property PACKAGE_PIN K17 [get_ports DDR3_CAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
set_property PACKAGE_PIN J17 [get_ports DDR3_S0_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
set_property PACKAGE_PIN J20 [get_ports DDR3_S1_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
set_property PACKAGE_PIN H20 [get_ports DDR3_ODT0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
set_property PACKAGE_PIN H18 [get_ports DDR3_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
set_property PACKAGE_PIN G17 [get_ports DDR3_TEMP_EVENT]
set_property IOSTANDARD SSTL15 [get_ports DDR3_TEMP_EVENT]
#NET  10N481                    LOC = P18  | IOSTANDARD=SSTL15; # Bank  38 VCCO - VCC1V5_FPGA - IO_L19P_T3_38
#NET  VTTVREF                   LOC = P17  | IOSTANDARD=SSTL15; # Bank  38 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_38
set_property PACKAGE_PIN M17 [get_ports 10N483]
set_property IOSTANDARD SSTL15 [get_ports 10N483]
set_property PACKAGE_PIN L17 [get_ports 10N484]
set_property IOSTANDARD SSTL15 [get_ports 10N484]
set_property PACKAGE_PIN N19 [get_ports 10N485]
set_property IOSTANDARD SSTL15 [get_ports 10N485]
set_property PACKAGE_PIN N18 [get_ports 10N486]
set_property IOSTANDARD SSTL15 [get_ports 10N486]
set_property PACKAGE_PIN M19 [get_ports 10N487]
set_property IOSTANDARD SSTL15 [get_ports 10N487]
set_property PACKAGE_PIN M18 [get_ports 10N488]
set_property IOSTANDARD SSTL15 [get_ports 10N488]
set_property PACKAGE_PIN P20 [get_ports 10N489]
set_property IOSTANDARD SSTL15 [get_ports 10N489]
set_property PACKAGE_PIN N20 [get_ports 10N490]
set_property IOSTANDARD SSTL15 [get_ports 10N490]
set_property PACKAGE_PIN L20 [get_ports 10N491]
set_property IOSTANDARD SSTL15 [get_ports 10N491]
set_property PACKAGE_PIN L19 [get_ports 10N492]
set_property IOSTANDARD SSTL15 [get_ports 10N492]
#NET  VRP_38                    LOC = K20  | IOSTANDARD=SSTL15; # Bank  38 VCCO - VCC1V5_FPGA - IO_25_VRP_38
#NET  VRN_39                    LOC = J16  | IOSTANDARD=SSTL15; # Bank  39 VCCO - VCC1V5_FPGA - IO_0_VRN_39
set_property PACKAGE_PIN C16 [get_ports DDR3_D30]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
set_property PACKAGE_PIN B16 [get_ports DDR3_D26]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
set_property PACKAGE_PIN B14 [get_ports DDR3_D24]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
set_property PACKAGE_PIN A14 [get_ports DDR3_DM3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
set_property PACKAGE_PIN C15 [get_ports DDR3_DQS3_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_P]
set_property PACKAGE_PIN C14 [get_ports DDR3_DQS3_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_N]
set_property PACKAGE_PIN D13 [get_ports DDR3_D28]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
set_property PACKAGE_PIN C13 [get_ports DDR3_D25]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
set_property PACKAGE_PIN D16 [get_ports DDR3_D31]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
set_property PACKAGE_PIN D15 [get_ports DDR3_D27]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
set_property PACKAGE_PIN E12 [get_ports DDR3_D29]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
#NET  VTTVREF                   LOC = D12  | IOSTANDARD=SSTL15; # Bank  39 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_39
#NET  10N563                    LOC = F16  | IOSTANDARD=SSTL15; # Bank  39 VCCO - VCC1V5_FPGA - IO_L7P_T1_39
set_property PACKAGE_PIN E15 [get_ports DDR3_D16]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
set_property PACKAGE_PIN E14 [get_ports DDR3_D19]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
set_property PACKAGE_PIN E13 [get_ports DDR3_D17]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
set_property PACKAGE_PIN H16 [get_ports DDR3_DQS2_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_P]
set_property PACKAGE_PIN G16 [get_ports DDR3_DQS2_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_N]
set_property PACKAGE_PIN G12 [get_ports DDR3_D21]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D21]
set_property PACKAGE_PIN F12 [get_ports DDR3_DM2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
set_property PACKAGE_PIN F15 [get_ports DDR3_D18]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
set_property PACKAGE_PIN F14 [get_ports DDR3_D22]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D22]
set_property PACKAGE_PIN G14 [get_ports DDR3_D23]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D23]
set_property PACKAGE_PIN G13 [get_ports DDR3_D20]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D20]
#NET  10N497                    LOC = H15  | IOSTANDARD=SSTL15; # Bank  39 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_39
set_property PACKAGE_PIN H14 [get_ports DDR3_D14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
set_property PACKAGE_PIN J13 [get_ports DDR3_D11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
set_property PACKAGE_PIN H13 [get_ports DDR3_D10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
set_property PACKAGE_PIN K12 [get_ports DDR3_DQS1_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS1_P]
set_property PACKAGE_PIN J12 [get_ports DDR3_DQS1_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS1_N]
set_property PACKAGE_PIN K15 [get_ports DDR3_DM1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
set_property PACKAGE_PIN J15 [get_ports DDR3_D15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
set_property PACKAGE_PIN K14 [get_ports DDR3_D8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
set_property PACKAGE_PIN K13 [get_ports DDR3_D9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
set_property PACKAGE_PIN L16 [get_ports DDR3_D12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
set_property PACKAGE_PIN L15 [get_ports DDR3_D13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
set_property PACKAGE_PIN L12 [get_ports DDR3_D7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
#NET  VTTVREF                   LOC = L11  | IOSTANDARD=SSTL15; # Bank  39 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_39
set_property PACKAGE_PIN M14 [get_ports DDR3_D3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
set_property PACKAGE_PIN L14 [get_ports DDR3_D2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
set_property PACKAGE_PIN N16 [get_ports DDR3_DQS0_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_P]
set_property PACKAGE_PIN M16 [get_ports DDR3_DQS0_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_N]
set_property PACKAGE_PIN N13 [get_ports DDR3_D1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
set_property PACKAGE_PIN M13 [get_ports DDR3_DM0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
set_property PACKAGE_PIN N15 [get_ports DDR3_D5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
set_property PACKAGE_PIN N14 [get_ports DDR3_D0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
set_property PACKAGE_PIN M12 [get_ports DDR3_D4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
set_property PACKAGE_PIN M11 [get_ports DDR3_D6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
set_property PACKAGE_PIN J11 [get_ports VRP_39]
set_property IOSTANDARD SSTL15 [get_ports VRP_39]
#NET  12N119                    LOC = AW2                       ; # Bank 111                 - MGTXTXP3_111
#NET  GND                       LOC = AW6                       ; # Bank 111                 - MGTXRXP3_111
#NET  12N118                    LOC = AW1                       ; # Bank 111                 - MGTXTXN3_111
#NET  GND                       LOC = AW5                       ; # Bank 111                 - MGTXRXN3_111
#NET  12N121                    LOC = AY4                       ; # Bank 111                 - MGTXTXP2_111
#NET  GND                       LOC = AY8                       ; # Bank 111                 - MGTXRXP2_111
#NET  12N120                    LOC = AY3                       ; # Bank 111                 - MGTXTXN2_111
#NET  12N117                    LOC = AW10                      ; # Bank 111                 - MGTREFCLK0P_111
#NET  GND                       LOC = AY7                       ; # Bank 111                 - MGTXRXN2_111
#NET  12N116                    LOC = AW9                       ; # Bank 111                 - MGTREFCLK0N_111
#NET  12N115                    LOC = BA9                       ; # Bank 111                 - MGTREFCLK1N_111
#NET  12N114                    LOC = BA10                      ; # Bank 111                 - MGTREFCLK1P_111
#NET  12N123                    LOC = BA2                       ; # Bank 111                 - MGTXTXP1_111
#NET  GND                       LOC = BA6                       ; # Bank 111                 - MGTXRXP1_111
#NET  12N122                    LOC = BA1                       ; # Bank 111                 - MGTXTXN1_111
#NET  GND                       LOC = BA5                       ; # Bank 111                 - MGTXRXN1_111
#NET  12N125                    LOC = BB4                       ; # Bank 111                 - MGTXTXP0_111
#NET  GND                       LOC = BB8                       ; # Bank 111                 - MGTXRXP0_111
#NET  12N124                    LOC = BB3                       ; # Bank 111                 - MGTXTXN0_111
#NET  GND                       LOC = BB7                       ; # Bank 111                 - MGTXRXN0_111
#NET  12N132                    LOC = AR2                       ; # Bank 112                 - MGTXTXP3_112
#NET  GND                       LOC = AP8                       ; # Bank 112                 - MGTXRXP3_112
#NET  12N133                    LOC = AR1                       ; # Bank 112                 - MGTXTXN3_112
#NET  GND                       LOC = AP7                       ; # Bank 112                 - MGTXRXN3_112
#NET  12N134                    LOC = AT4                       ; # Bank 112                 - MGTXTXP2_112
#NET  GND                       LOC = AR6                       ; # Bank 112                 - MGTXRXP2_112
#NET  12N135                    LOC = AT3                       ; # Bank 112                 - MGTXTXN2_112
#NET  12N130                    LOC = AT8                       ; # Bank 112                 - MGTREFCLK0P_112
#NET  GND                       LOC = AR5                       ; # Bank 112                 - MGTXRXN2_112
#NET  12N131                    LOC = AT7                       ; # Bank 112                 - MGTREFCLK0N_112
#NET  12N5                      LOC = W9                        ; # Bank 112                 - MGTRREF_112
#NET  12N128                    LOC = AU9                       ; # Bank 112                 - MGTREFCLK1N_112
#NET  12N129                    LOC = AU10                      ; # Bank 112                 - MGTREFCLK1P_112
#NET  12N136                    LOC = AU2                       ; # Bank 112                 - MGTXTXP1_112
#NET  GND                       LOC = AU6                       ; # Bank 112                 - MGTXRXP1_112
#NET  12N137                    LOC = AU1                       ; # Bank 112                 - MGTXTXN1_112
#NET  GND                       LOC = AU5                       ; # Bank 112                 - MGTXRXN1_112
#NET  12N138                    LOC = AV4                       ; # Bank 112                 - MGTXTXP0_112
#NET  GND                       LOC = AV8                       ; # Bank 112                 - MGTXRXP0_112
#NET  12N139                    LOC = AV3                       ; # Bank 112                 - MGTXTXN0_112
#NET  GND                       LOC = AV7                       ; # Bank 112                 - MGTXRXN0_112
#NET  13N97                     LOC = AL2                       ; # Bank 113                 - MGTXTXP3_113
#NET  13N95                     LOC = AJ6                       ; # Bank 113                 - MGTXRXP3_113
#NET  13N96                     LOC = AL1                       ; # Bank 113                 - MGTXTXN3_113
#NET  13N94                     LOC = AJ5                       ; # Bank 113                 - MGTXRXN3_113
set_property PACKAGE_PIN AM4 [get_ports SFP_TX_P]
set_property PACKAGE_PIN AL6 [get_ports SFP_RX_P]
set_property PACKAGE_PIN AM3 [get_ports SFP_TX_N]
set_property PACKAGE_PIN AH8 [get_ports SGMIICLK_Q0_P]
set_property PACKAGE_PIN AL5 [get_ports SFP_RX_N]
set_property PACKAGE_PIN AH7 [get_ports SGMIICLK_Q0_N]
set_property PACKAGE_PIN AK7 [get_ports SMA_MGT_REFCLK_N]
set_property PACKAGE_PIN AK8 [get_ports SMA_MGT_REFCLK_P]
set_property PACKAGE_PIN AN2 [get_ports SGMII_TX_P]
set_property PACKAGE_PIN AM8 [get_ports SGMII_RX_P]
set_property PACKAGE_PIN AN1 [get_ports SGMII_TX_N]
set_property PACKAGE_PIN AM7 [get_ports SGMII_RX_N]
set_property PACKAGE_PIN AP4 [get_ports SMA_MGT_TX_P]
set_property PACKAGE_PIN AN6 [get_ports SMA_MGT_RX_P]
set_property PACKAGE_PIN AP3 [get_ports SMA_MGT_TX_N]
set_property PACKAGE_PIN AN5 [get_ports SMA_MGT_RX_N]
set_property PACKAGE_PIN AG2 [get_ports PCIE_TX4_P]
set_property PACKAGE_PIN AD4 [get_ports PCIE_RX4_P]
set_property PACKAGE_PIN AG1 [get_ports PCIE_TX4_N]
set_property PACKAGE_PIN AD3 [get_ports PCIE_RX4_N]
set_property PACKAGE_PIN AH4 [get_ports PCIE_TX5_P]
set_property PACKAGE_PIN AE6 [get_ports PCIE_RX5_P]
set_property PACKAGE_PIN AH3 [get_ports PCIE_TX5_N]
set_property PACKAGE_PIN AD8 [get_ports SI5324_OUT_C_P]
set_property PACKAGE_PIN AE5 [get_ports PCIE_RX5_N]
set_property PACKAGE_PIN AD7 [get_ports SI5324_OUT_C_N]
#NET  13N40                     LOC = AF7                       ; # Bank 114                 - MGTREFCLK1N_114
#NET  13N41                     LOC = AF8                       ; # Bank 114                 - MGTREFCLK1P_114
set_property PACKAGE_PIN AJ2 [get_ports PCIE_TX6_P]
set_property PACKAGE_PIN AF4 [get_ports PCIE_RX6_P]
set_property PACKAGE_PIN AJ1 [get_ports PCIE_TX6_N]
set_property PACKAGE_PIN AF3 [get_ports PCIE_RX6_N]
set_property PACKAGE_PIN AK4 [get_ports PCIE_TX7_P]
set_property PACKAGE_PIN AG6 [get_ports PCIE_RX7_P]
set_property PACKAGE_PIN AK3 [get_ports PCIE_TX7_N]
set_property PACKAGE_PIN AG5 [get_ports PCIE_RX7_N]
set_property PACKAGE_PIN W2 [get_ports PCIE_TX0_P]
set_property PACKAGE_PIN Y4 [get_ports PCIE_RX0_P]
set_property PACKAGE_PIN W1 [get_ports PCIE_TX0_N]
set_property PACKAGE_PIN Y3 [get_ports PCIE_RX0_N]
set_property PACKAGE_PIN AA2 [get_ports PCIE_TX1_P]
set_property PACKAGE_PIN AA6 [get_ports PCIE_RX1_P]
set_property PACKAGE_PIN AA1 [get_ports PCIE_TX1_N]
#NET  14N526                    LOC = Y8                        ; # Bank 115                 - MGTREFCLK0P_115
set_property PACKAGE_PIN AA5 [get_ports PCIE_RX1_N]
#NET  14N527                    LOC = Y7                        ; # Bank 115                 - MGTREFCLK0N_115
#NET  14N474                    LOC = B11                       ; # Bank 115                 - MGTRREF_115
set_property PACKAGE_PIN AB7 [get_ports PCIE_CLK_QO_N]
set_property PACKAGE_PIN AB8 [get_ports PCIE_CLK_QO_P]
set_property PACKAGE_PIN AC2 [get_ports PCIE_TX2_P]
set_property PACKAGE_PIN AB4 [get_ports PCIE_RX2_P]
set_property PACKAGE_PIN AC1 [get_ports PCIE_TX2_N]
set_property PACKAGE_PIN AB3 [get_ports PCIE_RX2_N]
set_property PACKAGE_PIN AE2 [get_ports PCIE_TX3_P]
set_property PACKAGE_PIN AC6 [get_ports PCIE_RX3_P]
set_property PACKAGE_PIN AE1 [get_ports PCIE_TX3_N]
set_property PACKAGE_PIN AC5 [get_ports PCIE_RX3_N]
set_property PACKAGE_PIN P4 [get_ports FMC2_HPC_DP7_C2M_P]
set_property PACKAGE_PIN R6 [get_ports FMC2_HPC_DP7_M2C_P]
set_property PACKAGE_PIN P3 [get_ports FMC2_HPC_DP7_C2M_N]
set_property PACKAGE_PIN R5 [get_ports FMC2_HPC_DP7_M2C_N]
set_property PACKAGE_PIN R2 [get_ports FMC2_HPC_DP6_C2M_P]
set_property PACKAGE_PIN U6 [get_ports FMC2_HPC_DP6_M2C_P]
set_property PACKAGE_PIN R1 [get_ports FMC2_HPC_DP6_C2M_N]
set_property PACKAGE_PIN T8 [get_ports FMC2_HPC_GBTCLK1_M2C_C_P]
set_property PACKAGE_PIN U5 [get_ports FMC2_HPC_DP6_M2C_N]
set_property PACKAGE_PIN T7 [get_ports FMC2_HPC_GBTCLK1_M2C_C_N]
#NET  14N534                    LOC = V7                        ; # Bank 116                 - MGTREFCLK1N_116
#NET  14N535                    LOC = V8                        ; # Bank 116                 - MGTREFCLK1P_116
set_property PACKAGE_PIN T4 [get_ports FMC2_HPC_DP5_C2M_P]
set_property PACKAGE_PIN V4 [get_ports FMC2_HPC_DP5_M2C_P]
set_property PACKAGE_PIN T3 [get_ports FMC2_HPC_DP5_C2M_N]
set_property PACKAGE_PIN V3 [get_ports FMC2_HPC_DP5_M2C_N]
set_property PACKAGE_PIN U2 [get_ports FMC2_HPC_DP4_C2M_P]
set_property PACKAGE_PIN W6 [get_ports FMC2_HPC_DP4_M2C_P]
set_property PACKAGE_PIN U1 [get_ports FMC2_HPC_DP4_C2M_N]
set_property PACKAGE_PIN W5 [get_ports FMC2_HPC_DP4_M2C_N]
set_property PACKAGE_PIN K4 [get_ports FMC2_HPC_DP3_C2M_P]
set_property PACKAGE_PIN J6 [get_ports FMC2_HPC_DP3_M2C_P]
set_property PACKAGE_PIN K3 [get_ports FMC2_HPC_DP3_C2M_N]
set_property PACKAGE_PIN J5 [get_ports FMC2_HPC_DP3_M2C_N]
set_property PACKAGE_PIN L2 [get_ports FMC2_HPC_DP2_C2M_P]
set_property PACKAGE_PIN L6 [get_ports FMC2_HPC_DP2_M2C_P]
set_property PACKAGE_PIN L1 [get_ports FMC2_HPC_DP2_C2M_N]
set_property PACKAGE_PIN K8 [get_ports FMC2_HPC_GBTCLK0_M2C_C_P]
set_property PACKAGE_PIN L5 [get_ports FMC2_HPC_DP2_M2C_N]
set_property PACKAGE_PIN K7 [get_ports FMC2_HPC_GBTCLK0_M2C_C_N]
#NET  15N556                    LOC = M7                        ; # Bank 117                 - MGTREFCLK1N_117
#NET  15N557                    LOC = M8                        ; # Bank 117                 - MGTREFCLK1P_117
set_property PACKAGE_PIN M4 [get_ports FMC2_HPC_DP1_C2M_P]
set_property PACKAGE_PIN N6 [get_ports FMC2_HPC_DP1_M2C_P]
set_property PACKAGE_PIN M3 [get_ports FMC2_HPC_DP1_C2M_N]
set_property PACKAGE_PIN N5 [get_ports FMC2_HPC_DP1_M2C_N]
set_property PACKAGE_PIN N2 [get_ports FMC2_HPC_DP0_C2M_P]
set_property PACKAGE_PIN P8 [get_ports FMC2_HPC_DP0_M2C_P]
set_property PACKAGE_PIN N1 [get_ports FMC2_HPC_DP0_C2M_N]
set_property PACKAGE_PIN P7 [get_ports FMC2_HPC_DP0_M2C_N]
set_property PACKAGE_PIN F4 [get_ports FMC1_HPC_DP7_C2M_P]
set_property PACKAGE_PIN E6 [get_ports FMC1_HPC_DP7_M2C_P]
set_property PACKAGE_PIN F3 [get_ports FMC1_HPC_DP7_C2M_N]
set_property PACKAGE_PIN E5 [get_ports FMC1_HPC_DP7_M2C_N]
set_property PACKAGE_PIN G2 [get_ports FMC1_HPC_DP6_C2M_P]
set_property PACKAGE_PIN F8 [get_ports FMC1_HPC_DP6_M2C_P]
set_property PACKAGE_PIN G1 [get_ports FMC1_HPC_DP6_C2M_N]
set_property PACKAGE_PIN E10 [get_ports FMC1_HPC_GBTCLK1_M2C_C_P]
set_property PACKAGE_PIN F7 [get_ports FMC1_HPC_DP6_M2C_N]
set_property PACKAGE_PIN E9 [get_ports FMC1_HPC_GBTCLK1_M2C_C_N]
#NET  15N522                    LOC = AC9                       ; # Bank 118                 - MGTRREF_118
#NET  15N601                    LOC = G9                        ; # Bank 118                 - MGTREFCLK1N_118
#NET  15N600                    LOC = G10                       ; # Bank 118                 - MGTREFCLK1P_118
set_property PACKAGE_PIN H4 [get_ports FMC1_HPC_DP5_C2M_P]
set_property PACKAGE_PIN G6 [get_ports FMC1_HPC_DP5_M2C_P]
set_property PACKAGE_PIN H3 [get_ports FMC1_HPC_DP5_C2M_N]
set_property PACKAGE_PIN G5 [get_ports FMC1_HPC_DP5_M2C_N]
set_property PACKAGE_PIN J2 [get_ports FMC1_HPC_DP4_C2M_P]
set_property PACKAGE_PIN H8 [get_ports FMC1_HPC_DP4_M2C_P]
set_property PACKAGE_PIN J1 [get_ports FMC1_HPC_DP4_C2M_N]
set_property PACKAGE_PIN H7 [get_ports FMC1_HPC_DP4_M2C_N]
set_property PACKAGE_PIN B4 [get_ports FMC1_HPC_DP3_C2M_P]
set_property PACKAGE_PIN A6 [get_ports FMC1_HPC_DP3_M2C_P]
set_property PACKAGE_PIN B3 [get_ports FMC1_HPC_DP3_C2M_N]
set_property PACKAGE_PIN A5 [get_ports FMC1_HPC_DP3_M2C_N]
set_property PACKAGE_PIN C2 [get_ports FMC1_HPC_DP2_C2M_P]
set_property PACKAGE_PIN B8 [get_ports FMC1_HPC_DP2_M2C_P]
set_property PACKAGE_PIN C1 [get_ports FMC1_HPC_DP2_C2M_N]
set_property PACKAGE_PIN A10 [get_ports FMC1_HPC_GBTCLK0_M2C_C_P]
set_property PACKAGE_PIN B7 [get_ports FMC1_HPC_DP2_M2C_N]
set_property PACKAGE_PIN A9 [get_ports FMC1_HPC_GBTCLK0_M2C_C_N]
#NET  15N539                    LOC = C9                        ; # Bank 119                 - MGTREFCLK1N_119
#NET  15N538                    LOC = C10                       ; # Bank 119                 - MGTREFCLK1P_119
set_property PACKAGE_PIN D4 [get_ports FMC1_HPC_DP1_C2M_P]
set_property PACKAGE_PIN C6 [get_ports FMC1_HPC_DP1_M2C_P]
set_property PACKAGE_PIN D3 [get_ports FMC1_HPC_DP1_C2M_N]
set_property PACKAGE_PIN C5 [get_ports FMC1_HPC_DP1_M2C_N]
set_property PACKAGE_PIN E2 [get_ports FMC1_HPC_DP0_C2M_P]
set_property PACKAGE_PIN D8 [get_ports FMC1_HPC_DP0_M2C_P]
set_property PACKAGE_PIN E1 [get_ports FMC1_HPC_DP0_C2M_N]
set_property PACKAGE_PIN D7 [get_ports FMC1_HPC_DP0_M2C_N]
